1. Field of the Invention
This invention relates generally to communication systems and more particularly to wireless networks.
2. Related Art
Digital data can be transmitted over analog channels or wirelessly for communication to users. The channel over which data is communicated has several inherent difficulties. Corruption of transmitted data occurs additively or multiplicatively due to noise and other physical phenomena. A goal of the transmission and reception system is to communicate reliably and ably, despite these difficulties.
In order to communicate digital data over an analog channel, the data is modulated using, among other techniques, a form of pulse amplitude modulation. In pulse amplitude modulation (PAM), the amplitude of a pulsed carrier changes based on the signal information. The signal or useful information, therefore, is carried in the amplitude of the pulses of the carrier. A form of pulse amplitude modulate is quadrature amplitude modulation (QAM). QAM is an improvement over a traditional PAM, in that QAM increases the amount of data that can be transmitted within a particular channel. QAM is a form of PAM in which a plurality of bits are transmitted in a constellation, that can contain, for example 16 or 32 points. Typically, in a QAM, the signal changes both in the amplitude dimension and the phase dimension.
A typical communication system over an analog channel or wireless channel involves a receiver and a transmitter. In order to handle the channel uncertainty when the information is passed over the channel, the useful information is encoded with redundant bits to correct single and multiple bit errors as the information is received over the uncertain channel. At the transmitter, the encoding for forward error correction (FEC) is performed. In order to reduce the probability of block errors from occurring, the encoded information is passed over an interleaver, so that contiguous encoded bits are not transmitted adjacent to each other. The symbols are then mapped over a carrier frequency in a band through a form of frequency interleaving before being processed for transmission. On reception, a reverse process is undertaken: the received data is de-interleaved and then decoded. The decoded data is processed for error detection and check, and if necessary, a correction of data.
Typically, for a certain bandwidth and network architecture, a transmit data path exists as a hardware implementation of all of the components. These components perform the functions of encoding, stream parsing, QAM mapping, OFDM modulation and preamble processing before passing the processed data to an RF transceiver connected to an antenna. On the receive side, an antenna connected to an RF transceiver receives the information and subsequent components perform preamble processing, OFDM demodulation, QAM de-mapping, bit de-interleaving and decoding. Both receive and transmit data paths have a certain data width and operate at a certain clock speed to support a certain bandwidth.
With the increase in the demands of the interne, all sections of the network, including wireless LAN are going through a bandwidth explosion, necessitating an upgrade of the specifications to a higher bandwidth and with better and more reliable performance. For an equipment vendor in the networking area and particularly in the wireless LAN space, it is imperative to keep abreast with architectural changes driven by growth in demand for the bandwidth and develop products with reduced time to market and with competitive feature sets. For the vendors, it is increasingly difficult to spin a new generation of product architecture with each and every change in the specification.
In the evolutionary development of the 802.11 standard, the latest standard is referred to as 802.11ac for “very high throughput” (VHT). VHT transfers data in a 5 GHz band. Embodiments include RF signal bandwidths of up to 160 MHz and data rates of up to 6.933 Gbps. In one embodiment, maximum bandwidths can be 80 MHz or 160 MHz. More efficient signal processing schemes and data path design techniques are being deployed to reduce noise and improve the signal to noise ratio along with scaling the bandwidths to double or quadruple the data transfer rates.
Where a next generation network architecture with higher bandwidth is to be supported, several trade-off points are available to the system designer. The system designer performs under the constraints of managing recurring and non-recurring engineering costs, reduced time to market and faster adaptability to changing standards. There is no compromise however, on key aspects of supporting the higher specified bandwidth and maintaining backwards compatibility to be able to work with equipment that has not yet been upgraded. The system designer's work invariably involves a tradeoff between using the components designed for a previous generation and running it at same or higher speeds or redesigning the entire data path. Redesigning the entire data path presents substantial risks to time to market. The new design has to be functionally verified and confirmed that it complies with a set of specifications for function, reliability, mechanics and environment, among others. Running older designs at higher speeds is not always feasible as the design has been targeted to a certain clock speed for a certain target technology.
While some clock speedup is possible by way of upgrade of technology, it is not of the order of the scale by which the bandwidths are expanding from generation to generation. Further, where the design involves analog components along with digital components, as in a silicon implementation of an RF radio receiver and transmitter, the linear scaling of technology is not possible, as it is for a purely digital design. Accordingly, traditional solutions do not present optimal solutions for the system designer.